Semiconductor devices each functions as a high withstand voltage MOS transistor have been conventionally proposed. As shown in FIG. 15, the high withstand voltage MOS transistor is provided with a silicon substrate 71 which includes an isolation region 72 for element isolation and electric field relaxation layers 73. The silicon substrate 71 further has a gate electrode 75 and a gate oxidized film 74. The gate electrode 75 is formed in such a manner that two ends thereof respectively overlap the electric field relaxation layers 73, and the gate oxidized film 74 is interposed between the gate electrode 75 and the electric field relaxation layers 73. On two sides of the gate electrode 75, source and drain regions 76 having so-called offset structure is provided a certain distance away from the gate electrode 75. Usually, to ensure a high withstand voltage, the gate length and the size of the electric field relaxation layer 73 are increased to a certain degree, in the high withstand voltage MOS transistor having the above structure.
On the other hand, for example, Patent Citation 1 (Japanese Unexamined Patent Publication No. 251980/1992 (Tokukaihei 4-251980; Published on Sep. 8, 1992)) proposes a high withstand voltage MOS transistor using a trench for a purpose of achieving a higher integration. As shown in FIG. 16, to form the high withstand voltage MOS transistor, a trench 60 is first formed on an N-type semiconductor substrate 50, and then P-type impurity diffusion layers 61 are formed on side and bottom surfaces of the trench 60. Next, as shown in FIG. 17, the bottom surface of the trench 60 is further deepened to form a trench 62. Then, as shown in FIG. 18, an oxidized film 63 is formed through a thermal oxidation or the like on the outer layer including the side and bottom surfaces of the trench 62. Then, a polysilicon film is formed through a CVD method on the entire superior surface of the semiconductor substrate 50 including the trench 62. The polysilicon film is patterned into a gate electrode 64 through photo lithography and etching. A low concentration diffusion layer 65 for P-LDD is formed. At the ends of the gate electrode 64, side walls 66 are formed. Then, through a conventional manufacturing method, P-type high concentration impurity diffusion layers 67 are formed. Thus, a P-type high withstand voltage MOS transistor as shown in FIG. 18 and FIG. 19 is obtained.
The P-type high withstand voltage MOS transistor thus obtained has the gate electrode 64 which is formed so as to cover the trench 62. At the ends of the gate electrode 64, the side walls 66 are provided. Adjacently to the side walls 66, the P-type high concentration impurity layers 67 to become source and drain regions are arranged. The P-type high concentration impurity layers 67 and the trench 62 are surrounded by an isolation region 68 formed through LOCOS method. In a region where the gate electrode 64 overlaps the isolation region 68, a contact region 69 to be connected to metal wiring is formed.
Since this high withstand voltage MOS transistor has the P-type impurity diffusion layers 61 which serve as electric field relaxation layers on the side surfaces of the trench 62, an area taken by the transistor is reduced. However, since the trench 62 is formed by further deepening the trench 60 after the trench 60 is formed, the process of manufacturing becomes complicated. This consequently raises the production cost and decreases the yield.
Further, it is necessary to form the side wall on each side surface of the gate electrode 64, and to form the contact region 69 on the isolation region 68 for connecting the gate electrode 64 to metal wiring. This reduces an amount by which the high withstand voltage MOS transistor is downsized.
In order to solve the problem, for example, Japanese Unexamined Patent Publication No. 2004-39985 (Tokukai 2004-39985; Published on Feb. 5, 2004) (Patent Citation 2) proposes a high withstand voltage MOS transistor in which a drift diffusion region is formed on walls of a trench, by implanting ion at an oblique angle. As shown in FIG. 20, in the high withstand voltage MOS transistor, a trench 41 is formed on a semiconductor substrate 40, and a drift diffusion layer 42 is formed on the walls of the trench 41, by implanting ion at an oblique angle. At this point, the ion is not implanted to the bottom of the trench 41. This is because the edges at the top of the trench 41 block implantation of the ion into the bottom surface.
Then, as shown in FIG. 21, a gate oxidized film 43 is formed on the walls and the bottom surface of the trench 41, and a gate electrode 44 is buried into the trench 41. Then, through ion implantation, a high concentration impurity diffusion layer 45, an interlayer insulation film 46 and drain/source/gate electrode wiring 47 are formed. Thus, a high withstand voltage MOS transistor as shown in FIG. 21 is obtained.
The high withstand voltage MOS transistor shown in FIG. 21 allows a high integration, and its manufacturing method is simplified. However, since the gate electrode 44 is adjacent to the high concentration impurity diffusion layer 45, the withstand voltage of the high withstand voltage MOS transistor is deteriorated due to an effect from the electric field at the gate electrode 44. It is therefore difficult to achieve a higher withstand voltage.
Further, as shown in FIG. 20, in formation of the drift diffusion layer 42 by implantation of ion into the walls of the trench 41 at an oblique angle, the following relation is established: (b=a/tan θ), where: θ is an implantation angle at which ion is implanted to form the drift diffusion layer 42; a is a gate length (trench 41 width); and b is a length of the drift diffusion layer 42. Accordingly, determining of the depth of the trench 41 determines one gate length (trench 41 width). Accordingly, a circuit (e.g. an output circuit of a liquid crystal driver) which is largely affected by variation in characteristics of the transistor is not able to adopt the above-described downsized high withstand voltage transistor. This is because, when designing such a circuit, it is not possible to increase the gate length to reduce an effect of variation in the accuracy of processing in the manufacturing process.